1. Field of the Invention
Aspects of the present invention relate in general to an apparatus, system and method of microprocessor design. Further aspects relate to the design of processors augmented with application specific instructions, and include an apparatus, method, and computer-readable medium capable of fast and accurate measurement of the hardware cost of adding complex instructions to a microprocessor.
2. Background of the Invention
The programmability provided by a processor makes it a preferred platform for a range of applications such as desktop computing, digital photography, and mobile telephony. The programmability results in amortization of the non-recurring engineering cost, ability to provide value added services, and ability to evolve the product in the presence of changing standards. Unfortunately, the programmability offered by a general purpose, fixed instruction set processor is either inadequate to meet the performance requirement or wasteful of hardware. This is especially true for embedded applications such as digital photography and mobile telephony that have application-specific processing requirements.
Application-specific processors are able to deliver orders of magnitude increase in performance and reduce the hardware cost compared to a fixed instruction set processor. U.S. Pat. No. 6,477,683, granted to Killian et al., describes an automated processor generation system for designing a configurable processor. The engineering effort and methodology to discover, describe, and design processor extension and associated software is presented by A. Wang et al. in “Hardware/Software Instruction Set Configurability for System-on-Chip Processors” in the proceedings of Design Automation Conference, 2001. The existing approaches have focused on the software aspects such as: analysis of target application to identify code sections to optimize the instruction set; generation of software development tools for optimized instruction set; and improvement of processor cycle count performance after addition of new instructions. The existing approaches generates register-transfer level hardware description that decodes and executes new instructions, however, it relies on existing electronic design automation (EDA) tools to perform logical and physical design of the register-transfer description to implement the hardware in a standard cells-based integrated circuit silicon.
The hardware design iteration 100 for application-specific processors is shown in FIG. 1. A system architect profiles the application code to identify performance critical code sections. Next, the system architect designs new instructions, act 102, using an instruction extension language. The instruction extension description is translated into a synthesizable register transfer level hardware description, act 106, by a configurable processor generator 104. The register-transfer description is converted into a standard cells-based hardware description 108 using EDA tools including a standard cell library 10, act 110. The process of converting the register-transfer description into a standard cells-based description is very time consuming and resource intensive. If the measured hardware cost of the standard cells-based description does not meet the required specification at 110, the whole process of instruction definition, register-transfer level hardware generation, and hardware implementation is repeated. The turnaround time for hardware implementation is on the order of hours to days. Since the process of hardware cost determination is very lengthy, it limits the amount of exploration to determine the optimal instruction set extension. The limitation of the existing approach is that the hardware cost determination relies on completing the implementation, a slow process that prevents rapid exploration at the architectural-level.